The approaches described in this section could be pursued, but are not necessarily approaches that have been previously conceived or pursued. Therefore, unless otherwise indicated herein, the approaches described in this section are not prior art to the claims in this application and are not admitted to be prior art by inclusion in this section.
In-System Programmable (ISP) Flash memory devices are programmable logic devices (PLDs) that make use of electrically erasable and programmable Flash memory cells and are capable of being programmed or re-programmed while mounted on a system board. ISP refers to the entire process of programming a device in-system, and, therefore, encompasses the actions of erasing and verifying the design in the device in addition to the specific action of memory cell programming. ISP allows for speedier product development and facilitates the process of improving a PLD in a system.
Some ISP Flash devices contain a so-called Joint Test Action Group (JTAG) interface through which a user can program the device. This interface is a standard specified in “Institute of Electrical and Electronics Engineers (IEEE) Standard Test Access Port and Boundary-Scan Architecture”, IEEE Std 1149.1-1990 (includes IEEE Std 1149.1a-1993), published by the Institute of Electrical and Electronics Engineers, Inc. on Oct. 21, 1993. The JTAG standard creates a means of verifying the integrity of traces between components on an assembled printed circuit board by providing a standard architecture and a set of mandatory public instructions that all vendors claiming conformance to IEEE standard 1149.1 must support. A JTAG bus is a serial test bus that adds a Test Access Port (TAP) consisting of four pins to an integrated circuit (IC) or PLD (or five pins with an additional optional RESET pin). The four mandatory signals comprising the JTAG TAP are Test Clock (TCK), Test Mode Select (TMS), Test Data Input (TDI), and Test Data Output (TDO). JTAG provides access to interconnected digital cells on an IC with a method of access for test and diagnostics and the ability to do factory and remote testing and diagnostics. Furthermore, JTAG ISP also provides for software debugging and reducing “No-Fault-Found” problems.
JTAG ISP has several limitations that affect the time taken to perform the flash memory operations like read, write, and erase. One limitation is that the hardware programming cable protocol control and the handshaking mechanism between host machine and endpoint that is utilized in the PLD may introduce performance penalties in performing the flash memory operations. Even when using Universal Serial Bus (USB) protocol for USB Blaster or Ethernet protocol for Ethernet Blaster, performance may be limited by the JTAG frequency that a PLD device supports. In a typical set up JTAG ISP sends data through TDI pin in serial and receives data through TDO pin in serial. Therefore, single bit data transaction may not optimize potential flash programming performance. Furthermore, JTAG ISP provides no feedback to indication the completion of programming operations. Thus, the external host that is programming the flash through JTAG may have to wait the maximum time provided by manufacturer of the PLD device for programming every word. JTAG ISP is also not optimized to support multiple PLD chains through a single host. For example, a customer may wish to program four boards using a USB Blaster, where each board includes a PLD and a single device JTAG chain. The customer can either use four hosts (which may be computer systems) to optimize flash programming performance. However, this increases the cost of running multiple flash memory operations. The customer may also use a single host to connect the four JTAG chains (assuming there are no hardware USB-port limitations). However, sharing host resources over multiple endpoints may drastically reduce performance.